Acta Informatica Pragensia 2013, 2(1), 79-90 | DOI: 10.18267/j.aip.152762

Viacjadrová architektúra zameraná na akceleráciu výpočtov

Liberios Vokorokos, Eva Chovancová
Katedra počítačov a informatiky, Fakulta elektrotechniky a informatiky, Technická univerzita v Košiciach, Letná 9, 04001 Košice, Slovenská republika

Viacjadrové procesory je možné navrhnúť ako akcelerátor časovo-náročných výpočtov. Výskum v práci je zameraný na návrh architektúry urýchľujúcej výpočty v oblasti počítačového videnia. Práca poukazuje na možnosti návrhu viacjadrovej architektúry, pričom architektúra navrhovaného špecializovaného procesora je predstaviteľom Harvardskej architektúry. Navrhnutá architektúra umožňuje na základe paralelizácie výpočtov urýchliť časovo-náročné výpočty.

Keywords: viacjadrová architektúra, prahovanie, obraz, procesor, čip, mapovanie, paralelizácia

Acceleration based on multicore architecture

Multicore processors can be designed also as accelerator of time-consuming calculations. This work is focused on architecture design, which can accelerate computing in computer vision. In this paper are shown design possibilities for multicore architectures, whereby the specialized processor is proposed as representative of Harvard architecture. The proposed architecture based on computing parallelization allows accelerating the time-consuming calculations in computer vision.

Keywords: multicore architecture, thresholding, image, processor, chip, mapping, parallelization

Received: March 26, 2013; Revised: May 16, 2013; Accepted: June 1, 2013; Published: June 29, 2013  Show citation

ACS AIP APA ASA Harvard Chicago Chicago Notes IEEE ISO690 MLA NLM Turabian Vancouver
Vokorokos, L., & Chovancová, E. (2013). Acceleration based on multicore architecture. Acta Informatica Pragensia, 2(1), 79-90. doi: 10.18267/j.aip.15
Download citation
  • BibTeX (.bib)
  • Bookends (.ris)
  • EasyBib (.ris)
  • EndNote (.enw)
  • EndNote 8 (.xml)
  • ISI WoS (.isi)
  • Medlars (.medlars)
  • Mendeley (.ris)
  • MODS (.xml)
  • Papers (.ris)
  • RefWorks (.txt)
  • RefManager (.ris)
  • RIS (.ris)
  • MS Word (.xml)
  • Zotero (.ris)
    • Open full article

    References

    1. AKHTER, S. Multi-core programming: increasing performance through software multi-threading. 1. vyd. New York: Intel Press, 2006. ISBN 0-9764832-4-6.
    2. IEEE signal processing magazine [online]. Univ Politecnica de Madrid, 2009 [cit. 2013-02-18]. ISSN 1053-5888. Dostupné z: http://web.eecs.umich.edu/~blakeg/docs/aSurveyofMulticoreProcessors.pdf
    3. PARELEC 2006: International Symposium on Parallel Computing in Electrical Engineering : 13-17 September 2006, Bialystok, Poland. Multi-Core Processors: New Way to Achieve High System Performance. 2006, č. 6. Dostupné z: http://www.researchgate.net/publication/220959927_Multi-Core_Processors_New_Way_to_Achieve_High_System_Performance/file/5046351838467bcb9f.pdf
    4. HENNESSY, John L. Computer architecture: a quantitative approach [online]. 4th ed. San Francisco: Morgan Kaufmann, 2007, 1 sv. (různé stránkování) [cit. 2013-06-17]. ISBN 01-237-0490-1.
    5. HLAVÁČ, Václav a Milan ŠONKA. Počítačové vidění. Praha: Grada, 1992, 272 s. ISBN 80-854-2467-3.
    6. MAJUMDER, Bhabatosh Chanda and Dwijesh Dutta. Digital image processing and analysis. Eastern economy ed. New Delhi: Prentice Hall of India, 2005. ISBN 81-203-1618-5.
    7. KUMAR, R, V ZYUBAN a D. M. TULLSEN. DEPT. OF COMPUT. SCI. & ENG., California Univ., San Diego, CA, USA. Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling. 2005. ISBN 0-7695-2270-X.
    8. SPAA 2006: eighteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures : July 30-August 2, 2006, Cambridge, Massachusetts, USA. New York: ACM Press, c2006. ISSN 1-59593-452-9. Dostupné z: http://cseweb.ucsd.edu/users/swanson/papers/SPAA2006WaveScalar.pdf
    9. NURMI, J. Processor design system-on-chip computing for ASICs and FPGAs. Online-Ausg. Dordrecht: Springer, 2007. ISBN 978-140-2055-300. Go to original source...
    10. PARKER, J.R. a Kostas Terzidis TECHNICAL EDITOR. Algorithms for image processing and computer vision. 2nd ed. Indianapolis, Ind: Wiley Pub, 2010. ISBN 11-180-2188-6.
    11. GONZALEZ, Rafael C a Richard E WOODS. Digital image processing. 3rd ed. Upper Saddle River: Pearson, c2008, xxii, 954 s. ISBN 01-316-8728-X.
    12. VOKOROKOS, L., B. MADOŠ, A. BALÁŽ a N. ÁDAM. Architecture of multi-core computer with dáta driven computation model. Acta Electrotechnica et Informatica. 2010, s. 20-23.
    13. VOKOROKOS, L. Princípy architektúr počítačov riadených tokom údajov. Košice: elfa, s.r.o., 2008. ISBN 978-80-8086-075-2.
    14. YOUNG, Roger. How computers work: processor and main memory. 2nd ed. S.l.: Roger Young, 2009. ISBN 14-421-1398-7.

    This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 International License (CC BY 4.0), which permits use, distribution, and reproduction in any medium, provided the original publication is properly cited. No use, distribution or reproduction is permitted which does not comply with these terms.


    Return to the content